FIG. 1 contains a block diagram of a conventional semiconductor memory device with data input/output organization defined in multiples of nine bits. The semiconductor memory device 10 includes eight memory arrays MAT0 to MAT7 that are arranged in regions of four rows and two columns. FIG. 2 is a detailed block diagram of a memory array of FIG. 1, for example, memory array MAT0. Referring to FIGS. 1 and 2, each of the memory arrays includes a plurality of memory blocks BLK0 to BLK7, a main row decoder circuit MRD, section row decoder circuits SRD, a column decoder & column gate block Y-DEC & Y-GATE and a sense amplifier and write driver block SA & WD.
Referring to FIG. 2, the main row decoder circuit MRD selectively drives main word lines that are arranged in the row direction (not shown). Each of the section row decoder circuits SRD selectively drives section word lines of corresponding memory blocks. The column decoder and column gate block Y-DEC & Y-GATE selects columns of the selected memory block, for example, nine columns in the case of data input/output organization in multiples of nine (hereinafter “×9”), and electrically connects the selected columns to the sense amplifier and write driver block SA & WD.
During a read operation, the sense amplifier and write driver block SA & WD senses data from selected memory block through selected rows, and the sensed data is transferred to a data bus MDL. In FIG. 2, a data bus comprises nine data lines MDL0 to MDL8. During a write operation, the sense amplifier and write driver block SA & WD transfers write data on the data bus MDL to the selected columns of the selected memory block through the column decoder and column gate block Y-DEC & Y-GATE.
FIG. 3 contains a detailed block diagram of a memory block BLK of FIG. 2. FIG. 3 shows the memory block and its peripheral circuit blocks as illustrated in FIG. 2. Referring to FIG. 3, a memory block BLK comprises nine memory block segments IO0 to IO8. A column decoder and column gate block Y-DEC & Y-GATE is a column selection circuit, and it selects one of the columns of each memory block segment IO0 to IO8. That is, nine columns are selected. During a read operation, sense amplifiers SA0 to SA8 sense one bit data from respective memory block segments IO0 to IO8 through the corresponding selected columns, and the selected nine-bit data is transferred to the corresponding data lines.
A read operation of the semiconductor memory device with data input/output organization in multiples of 18 (×18), 36 (×36) or 72 (×72) will be described more fully below. As discussed above, a semiconductor memory device 10 in FIG. 1 comprises eight memory arrays and each array comprises eight memory blocks BLK0 to BLK7,and each memory block comprises nine memory block segments IO0 to IO8.
FIG. 4A shows a method for outputting data relating to a ×72 single data rate (SDR) read operation or a ×36 double data rate DDR read operation. During a ×72 SDR read operation, nine bits of data are read simultaneously in each memory array and eventually seventy-two bits of data will be simultaneously output externally. During a ×36 DDR read operation, nine-bit data is read simultaneously in each memory array as in the ×72 SDR read operation. However, half of the seventy-two bits of data (thirty-six bits) is output externally in synchronization with the rising edge (or falling edge) of a clock signal and the other half (thirty-six bits) is output externally in synchronization with the falling edge (or rising edge) of the clock signal.
FIG. 4B contains a block diagram showing a data output scheme relating to a ×36 SDR read operation or a ×18 DDR read operation. During a ×36 SDR read operation, nine bits of data are simultaneously read in each memory array. Half of the eight memory arrays MAT0 to MAT7 should be selected in order to output thirty-six bits of data externally. As shown in FIG. 4B, the selection of the memory arrays is executed by a multiplexing method. Four multiplexors are required in order to select four memory arrays from the eight memory arrays. For example, a multiplexor MUX0 selects one of the two memory arrays MAT0, MAT2 and a multiplexor MUX1 selects one of the two memory arrays MAT1, MAT3 to output the nine bit-data from the selected memory arrays. A multiplexor MUX2 selects one of the two memory arrays MAT4, MAT6 and outputs the nine-bit data from the selected memory array. A multiplexor MUX3 selects one of the two memory arrays MAT5, MAT7 and outputs the nine-bit data from the selected memory array. Thus, thirty-six bits of data are output externally by the multiplexing method. In the case of a ×18 DDR read operation, half (eighteen bits) of the thirty-six-bit data is output externally in synchronization with the rising edge (or falling edge) of a clock signal and the other half (eighteen bits) is output externally in synchronization with the falling edge (or rising edge) of the clock signal.
FIG. 4C contains a block diagram showing a data output scheme relating to a ×18 SDR read operation or a ×9 DDR read operation. In this approach, six multiplexors MUX0 to MUX5 are used for the purpose of a ×18 SDR read operation. As shown in FIG. 4C, eighteen bits of data may be output externally by a two-stage multiplexing method. Similarly, in the case of a ×9 DDR read operation, half (nine bits) of the eighteen bits of data are output externally in synchronization with the rising edge (or falling edge) of a clock signal and the other half (nine bits) are output externally in synchronization with the falling edge (or rising edge) of the clock signal.
As described above, the nine-bit data is always read from each memory array (or selected memory array). Thus, a semiconductor memory device as shown in FIG. 1 has as a drawback that the device performance or operating characteristics are changed depending on the data input/output organization (×9, ×18, ×36 or ×72). The reason is that data is selectively output using a multiplexing method. For example, during the ×72 SDR/×36 DDR read operation, as shown in FIG. 4A, the selection of memory arrays is not executed using a multiplexing method. On the other hand, during the ×36/×18 SDR read operation or the ×18/×9 DDR read operation, as shown in FIGS. 4B and 4C, the selection of memory arrays is executed using a multiplexing method. The device performance is changed depending on the data input/output organization (×9, ×18, ×36 or ×72). Therefore, it is difficult for the semiconductor memory device as shown in FIG. 1 to maintain uniform performance or uniform operating characteristics regardless of the data input/output organization.